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Resistive Random-Access Memory (ReRAM) is an interesting emerging memory technology to replace conventional memory devices. ReRAM offers many attractive advantages like densest data storage, non-volatility, fast data access and scalable. Although potentially becoming the main emerging memory, ReRAM still prone to have a defect and fault. Nevertheless, because ReRAM uses a non-CMOS device as its memory cells, any defect might behave differently than the ones happen in the existing semiconductor memories. It means that the available memory tests might not detect defective ReRAM cells, leading to a low quality of manufactured ReRAM products. This paper presents the study of how the ReRAM cells behave when they are impacted by bridge defects. Such a defective behavior is required to develop the efficient memory test. A SPICE simulation was carried out using the Silvaco EDA tools. The simulation shows that bridge defects causes the impacted ReRAM cells to change the stored bit at defect values much lower than the value occur in existing semiconductor memories. This analysis confirms that a new memory test is desired.