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As transistor’s density and dimension have been rapidly shrunk down in every year onwards, it is difficult to design a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) that possesses minimal short channel effect (SCE) problems. One of the most recognized MOSFET architecture which has the ability to circumvent SCE is known as Vertical Double Gate (DG) MOSFET device. The presence of two gates are capable of doubling the channel coupling in Vertical DG-MOSFET device, thus resulting in higher current density. This paper presents a study in which an attempt has been made to virtually design the Ultrathin Pillar (UTP) Vertical Double Gate (VDG) MOSFET device for low power (LP) technology requirements by utilizing SILVACO TCAD tools. Three novel designs which are known as UTP VDG-MOSFET, UTP Silicon-on-insulator (SOI) VDG-MOSFET and UTP Polysilicon-on-insulator (POI) VDG-MOSFET are introduced in order to compare their electrical performance. From the retrieved results, it is observed that UTP POI VDG-MOSFET device is the most suitable design for low power application in which its threshold voltage (V_TH) and drive current (I_ON) values are correspondingly at 0.419 V and 704.6 µA/µm. These values are observed to be the closest value to the International Technology Roadmap Semiconductor (ITRS) 2013 specification.